1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and, more particularly, to the method of manufacturing the semiconductor device provided with a dual damascene wiring structure.
2. Description of the Related Art
In LSI (Large Scale Integrated) circuits such as micro-processors, memories and like, there is substantial incentive toward higher levels of integration density and design rules permitting smaller minimum feature sizes for individual circuit components or devices. In other words, as a semiconductor industry moves toward smaller and smaller device dimensions, a greater density of devices per silicon substrate is required. As device dimensions shrink, each of wires (wiring lines) extending from individual active areas also shrinks in width and in wiring pitch, wherein the wiring pitch is a distance between two adjacent wiring lines. Due to this, these wiring lines are closely packed to increase their wiring density. Further, since the wiring density has increased described above, a so-called xe2x80x9cmultilevel metallization technologyxe2x80x9d has been developed and employed, wherein a plurality of layers each of which has a wiring line and a thickness are stacked together into a stack to form a semiconductor device.
In the LSI circuits described above, shrinking of the wiring pitch leads to an increase in interwiring capacitance, which considerably affects particularly a high-speed type of LSI circuits in operation speed. In order to prevent the interwiring capacitance from increasing, it is so devised that an interlayer insulation film formed between two adjacent wiring layers is constructed of a low dielectric constant film. Further, operation speed depends on a wiring resistance. In general, heretofore, wiring materials used in the semiconductor device provided with LSI circuits have been aluminum (Al) or an aluminum-based alloy containing aluminum as its main component, wherein aluminum or the aluminum-based alloy is hereinafter referred to as an aluminum-based metal. However, in order to increase operation speed, it is necessary to use a conductive material which is smaller in electric resistance than the aluminum-based metal.
As a result, copper (Cu) which is smaller in electric resistance than the aluminum-based metal has been widely used in place of the aluminum-based metal.
On an other hand, as one of conventional structures adapted for use with a fine wiring line in a multilevel interconnection, there is known a dual damascene wiring structure. In this dual damascene wiring structure: a Cu underlying wiring line is previously formed on a semiconductor substrate; an interlayer insulation film is then formed on the semiconductor substrate through the Cu underlying wiring line; and, both a via hole and a trench for forming an overlying wiring line (hereinafter referred to as an overlying wiring trench) are formed in the interlayer insulation film and filled with Cu (copper) to form a Cu via contact and a Cu overlying wiring line, respectively; whereby the Cu underlying wiring line is electrically connected with the Cu overlying wiring line through the Cu via contact.
FIGS. 7A-7F and 8A-8E are views showing a series of process steps of a conventional method of manufacturing a semiconductor device provided with the dual damascene wiring structure such as that described above. Hereinbelow, with reference to FIGS. 7A-7F and 8A-8E, the conventional method of manufacturing the semiconductor device will be described in order of its process steps.
First, as shown in FIG. 7A, a Cu wiring line 51 is formed on a semiconductor substrate (not shown) as an underlying wiring line. Formed on the Cu wiring line 51 by a plasma CVD (chemical vapor deposition) process of a parallel flat plate type is a Pxe2x80x94SiN (plasma silicon nitride) film 52 which has a film thickness of approximately 50 nm. After formation of the Pxe2x80x94SiN film 52, an organic polymer film 53 having a film thickness of approximately 400 nm is formed on the Pxe2x80x94SiN film 52 by a spin coating process. Then, in an atmosphere of nitrogen gas, the semiconductor substrate is subjected to a baking process which is performed at a temperature of approximately 400xc2x0 C. for approximately one hour. After that, a Pxe2x80x94SiO2 (plasma silicon oxide) film 54 having a film thickness of approximately 100 nm is formed on the organic polymer film 53 by the plasma CVD process. Here, the Pxe2x80x94SiN film 52, the organic polymer film 53 and the Pxe2x80x94SiO2 film 54 serve as a Cu diffusion barrier film, a low dielectric constant film and an insulation protective film, respectively. Further, the Pxe2x80x94SiN film 52, the organic polymer film 53 and the Pxe2x80x94SiO2 film 54 are stacked into a stack to form an interlayer insulation film.
Next, as shown in FIG. 7B, a photoresist is applied to an upper surface of the Pxe2x80x94SiO2 film 54 to form a photoresist film on the Pxe2x80x94SiO2 film 54. After that, as will be described later, the thus formed photoresist film is patterned to form a first photoresist film 55 which has a pattern for forming a via hole. Then, as shown in FIG. 7C, using the first photoresist film 55 as a mask, a dry etching process is performed to selectively remove the Pxe2x80x94SiO2 film 54. Subsequent to this, as shown in FIG. 7D, using the first photoresist film 55 as a mask, a plasma etching process employing an oxygen-based gas is performed to selectively remove the organic polymer film 53 in a manner such that a hole 56 having a width of W1 and forming a part of the via hole is formed. Further, the first photoresist film 55 is removed by an ashing process when the organic polymer film 53 is selectively removed. In other words, the ashing process of the first photoresist film 55 is performed through an anisotropic plasma ashing treatment.
Next, as shown in FIG. 7E, a photoresist is applied to an upper surface of the Pxe2x80x94SiO2 film 54 to form a photoresist film on the Pxe2x80x94SiO2 film 54. After that, as will be described later, the thus formed photoresist film is patterned to form a second photoresist film 57 which has a pattern for forming an overlying wiring trench for forming an overlying wiring trench 58. Then, as shown in FIG. 7F, using the second photoresist film 57 as a mask, a dry etching process is performed to selectively remove the Pxe2x80x94SiO2 film 54. Subsequent to this, using the second photoresist film 57 as a mask, an oxygen plasma etching process is performed to selectively remove the organic polymer film 53 in a manner such that the overlying wiring trench 58 which has a width of W2 ( greater than W1) and is smaller in depth than the hole 56. Further, the second photoresist film 57 is also removed by an ashing process when the organic polymer film 53 is selectively removed, as is in a case of the first photoresist film 55. In other words, the ashing process of the second photoresist film 57 is performed through anisotropic plasma ashing treatment.
Then, as shown in FIG. 8A, by a plasma etching process, the Pxe2x80x94SiN film 52 is etched back to selectively expose the Cu wiring line 51. As a result, the hole 56 extends to a top surface of the Cu wiring line 51 thus exposed, so that a via hole 59 is formed. Then, as shown in FIG. 8B, by an ion sputtering process, a TaN (tantalum nitride) film 60 is formed over an entire surface of substrate including both the overlying wiring trench 58 and the via hole 59. After that, as shown in FIG. 8C, by a sputtering process, a Cu seed film 61 having a film thickness of approximately 50 nm is formed on the TaN film 60.
Next, as shown in FIG. 8D, by a plating process, a Cu-plated film 62 having a film thickness of approximately 800 nm is formed on the Cu seed film 61. After that, as shown in FIG. 8E, the Cu-plated film 62, the Cu seed film 61 and the TaN film 60, all of which are formed above a top surface of the Pxe2x80x94SiO2 film 54, are removed by a CMP (chemical mechanical polishing) process, so that the top surface of the Pxe2x80x94SiO2 film 54 is planarized to complete a dual damascene wiring structure, in which structure both the overlying wiring trench 58 and the via hole 59 are filled with the Cu-plated film 62.
The following problem is inherent in the conventional method of manufacturing the semiconductor device.
Namely, in the conventional method: when the photoresist films having been used in forming the via hole and the overlying wiring trench are removed, the low dielectric constant film is subjected to the anisotropic plasma ashing treatment, which tends to produce residue of the photoresist films. Such residue raises the problem inherent in the conventional method.
More specifically: as shown in FIG. 7D, by the plasma etching process using the oxygen-based gas, when the organic polymer film 53 forming the low dielectric constant film is selectively removed at a time when the first photoresist film 55 is removed; and, further, as shown in FIG. 7F, by the plasma etching process using the oxygen-based gas, when the organic polymer film 53 forming the low dielectric constant film is selectively removed at a time when the second photoresist film 57 is removed, the residue of each of the first photoresist film 55 and second photoresist film 57 is apt to be produced. The thus produced residue affects the remaining processes subsequent to the plasma etching processes, which makes it difficult to produce a good quality dual damascene structure.
In order to prevent the residue of each of the first photoresist film 55 and second photoresist film 57 from being produced, each of the first photoresist film 55 and second photorsist film 57 is subjected to an over-ashing process so that substantially all of the first photoresist film 55 and second photoresist film 57 are removed from the substrate. However, such removal of the first photoresist film 55 and second photoresist film 57 tends to deform each of the via hole 59 and the overlying wiring trench 58. Due to this, it is disadvantageous to perform such over-ashing process.
Further, in removing each of the first photoresist film 55 and second photoresist film 57, it is effective to perform an isotropic plasma ashing treatment in place of the anisotropic plasma ashing treatment. However, the isotropic plasma ashing treatment is also problematic since it suffers from the above-mentioned disadvantages.
In view of the above, it is an object of the present invention to provide a method of manufacturing a semiconductor device, wherein: when a plurality of photoresist films each used for forming each of a via hole and an overlying wiring trench are removed, a good quality dual damascene wiring structure is formed by preventing a low dielectric constant film from being subjected to a plasma ashing treatment.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an underlying wiring line made of copper or a conductive material containing copper as its main component is formed in a semiconductor substrate; after that, an interlayer insulation film including a low dielectric constant film is formed on the semiconductor substrate; an overlying wiring trench and a via hole are formed in the interlayer insulation film; and, the overlying wiring trench and the via hole are filled with copper or a conductive material containing copper as its main component to form an overlying wiring line and a via contact, the method including the steps of:
forming a metal mask on the interlayer insulation film;
subsequently forming a first photoresist film and a second photoresist film on the metal mask, wherein the first photoresist film and the second photoresist film are patterned to form the via hole and the overlying wiring trench, respectively;
patterning the metal mask according to a pattern of each of the first photoresist film and the second photoresist film; and
removing the first photoresist film and the second photoresist film prior to patterning of the interlayer insulation film, wherein the patterning is performed using the metal mask to form the via hole and the overlying wiring trench in the interlayer insulation film.
Also, according to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an underlying wiring line made of copper or a conductive material containing copper as its main component is formed in a semiconductor substrate; after that, an interlayer insulation film including a low dielectric constant film is formed on the semiconductor substrate; an overlying wiring trench and a via hole are formed in the interlayer insulation film; and, the overlying wiring trench and the via hole are filled with copper or a conductive material containing copper as its main component to form an overlying wiring line and a via contact, the method including:
a metal mask forming step for forming a metal mask on the interlayer insulation film;
a first photoresist film forming step for forming a first photoresist film on the metal mask, the first photoresist film having been patterned to have a pattern for forming the via hole;
a first photoresist film removing step for removing the first photoresist film by an isotropic plasma ashing treatment after the metal mask is patterned to have a same pattern as that of the first photoresist film;
a second photoresist film forming step for forming a second photoresist film on the metal mask, the second photoresist film having been patterned to have a pattern for forming the overlying wiring trench;
a second photoresist film removing step for removing the second photoresist film by the isotropic plasma ashing treatment after the metal mask is patterned to have a same pattern as that of the second photoresist film; and
an interlayer insulation film patterning step for sequentially patterning the interlayer insulation film by using the metal mask to sequentially form the via hole and the overlying wiring trench.
Also, according to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an underlying wiring line made of copper or a conductive material containing copper as its main component is formed in a semiconductor substrate; after that, an interlayer insulation film including a low dielectric constant film is formed on the semiconductor substrate; an overlying wiring trench and a via hole are formed in the interlayer insulation film; and, the overlying wiring trench and the via hole are filled with copper or a conductive material containing copper as its main component to form an overlying wiring line and a via contact, the method including:
a metal mask forming step for forming a metal mask on the interlayer insulation film, the metal mask being constructed of a multilayered element, the multilayered element having a first metal mask and a second metal mask;
a first photoresist film forming step for forming a first photoresist film on the metal mask, the first photoresist film having been patterned to have a pattern for forming the via hole;
a first photoresist film removing step for removing the first photoresist film by an isotropic plasma ashing treatment after the first metal mask and the second metal mask are patterned to have a same pattern as that of the first photoresist film;
a second photoresist film forming step for forming a second photoresist film on the metal mask, the second photoresist film having been patterned to have a pattern for forming the overlying wiring trench;
a second photoresist film removing step for removing the second photoresist film by an isotropic plasma ashing treatment after the second metal mask of the metal mask is patterned to have a same pattern as that of the second photoresist film; and
an interlayer insulation film patterning step for sequentially patterning the interlayer insulation film by using the metal mask to sequentially form the via hole and the overlying wiring trench.
In the foregoing second aspect or third aspect, a preferable mode is one wherein the interlayer insulation film is formed through: a first step for forming a Cu diffusion barrier film on the underlying wiring line; a second step for forming the low dielectric constant film on the Cu diffusion barrier film; and, a third step for forming an insulation protective film on the low dielectric constant film.
Also, a preferable mode is one wherein the metal mask is made of a material selected from a group consisting of: tungsten nitride; tantalum; tungsten; tantalum nitride; titanium; titanium nitride; and, tungsten silicide.
Also, a preferable mode is one wherein the Cu diffusion barrier film is made of a material selected from a group consisting of: plasma silicon nitride; and, plasma silicon carbide.
Further, a preferable mode is one wherein the low dielectric constant film is made of a material selected from a group consisting of: organic polymer; HSQ (Hydrogen Silsesquioxane); organic SOG (Spin on Glass); and, porous silica.
Still further, a preferable mode is one wherein, the insulation protective film is made of a material selected from the group consisting of: plasma silicon oxide; plasma silicon nitride; plasma silicon oxynitride; and, plasma silicon carbide.
With the above first aspect and second aspect, after formation of the metal mask on the interlayer insulation film including the low dielectric constant film, the first photoresist film and the second photoresist film are sequentially formed on the metal mask, wherein the first photoresist film and the second photoresist film are patterned to have patterns for forming the via hole and the overlying wiring trench, respectively; then the metal mask is patterned according to a pattern of each of the first and the second photoresist film; and, after that, the interlayer insulation film is patterned using the metal mask to form the via hole and the overlying wiring trench in the interlayer insulation film. Consequently, in patterning the interlayer insulation film, it is possible not to use the first photoresist film and the second photoresist film.
Also, with the configuration of the above third aspect, the metal mask constructed of the multilayered element having the first metal mask and the second metal mask is formed on the interlayer insulation film including the low dielectric constant film; then, the first photoresist film and the second photoresist film are sequentially formed on the metal mask, wherein the first photoresist film has been patterned to have a pattern for forming the via hole, and second photoresist film has been patterned to have a pattern for forming the overlying wiring trench; after that, the interlayer insulation film is patterned using the multilayered element to sequentially form the via hole and the overlying wiring trench. Consequently, it is possible not to use the first photoresist film and the second photoresist film in patterning the interlayer insulation film.
As a result, when individual photoresist films having been used to form the via hole and the overlying wiring trench are removed, it is possible to prevent the low dielectric constant film from being subjected to the plasma ashing treatment, which makes it possible for the method of the present invention to produce the high quality dual damascene structure.